In designing a semiconductor circuit such as a field programmable gate array (FPGA) or the like, there have been known various techniques for facilitating verification of the presence or absence of a timing error of a critical signal path or the like. For example, there has been known a technique for facilitating selection of a signal path by a designer by displaying a calculation result of a delay amount of a signal path as a list on a display unit (see, e.g., Japanese Laid-Open Patent Publication No. 08-278998). In addition, there has been known a technique for facilitating a grasp a range where a critical signal path exists by grouping delay values of wiring in a given range and displaying a bar graph depicting the number of wirings corresponding to the delay values (see, e.g., Japanese Laid-Open Patent Publication No. 2003-030264).
In recent years, as the scale of circuits mounted on a semiconductor device such as an FPGA increases with the progress of miniaturization and higher functionality of the semiconductor device, the number of timing errors occurring at the time of circuit designing increases. Such increase in the number of timing errors may result in a complicated examination on the countermeasures to eliminate the timing error, which may result in an increase in man-hours.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication Nos. 08-278998 and 2003-030264.